Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.
| Name | Vendor | Start Version | End Version |
|---|---|---|---|
| Red Hat Enterprise Linux 8 | RedHat | kernel-0:4.18.0-553.16.1.el8_10 | * |
| Red Hat Enterprise Linux 9 | RedHat | kernel-0:5.14.0-427.40.1.el9_4 | * |
| Red Hat Enterprise Linux 9 | RedHat | kernel-0:5.14.0-427.40.1.el9_4 | * |
| Red Hat Enterprise Linux 9 | RedHat | microcode_ctl-4:20240910-1.el9_5 | * |
| Red Hat Enterprise Linux 9.2 Extended Update Support | RedHat | kernel-0:5.14.0-284.88.1.el9_2 | * |
| Red Hat Enterprise Linux 9.2 Extended Update Support | RedHat | kernel-rt-0:5.14.0-284.88.1.rt14.373.el9_2 | * |
| Intel-microcode | Ubuntu | bionic | * |
| Intel-microcode | Ubuntu | esm-infra-legacy/trusty | * |
| Intel-microcode | Ubuntu | esm-infra/bionic | * |
| Intel-microcode | Ubuntu | esm-infra/xenial | * |
| Intel-microcode | Ubuntu | focal | * |
| Intel-microcode | Ubuntu | jammy | * |
| Intel-microcode | Ubuntu | mantic | * |
| Intel-microcode | Ubuntu | trusty | * |
| Intel-microcode | Ubuntu | trusty/esm | * |
| Intel-microcode | Ubuntu | xenial | * |
In many processor architectures an exception, mis-speculation, or microcode assist results in a flush operation to clear results that are no longer required. This action prevents these results from influencing architectural state that is intended to be visible from software. However, traces of this transient execution may remain in microarchitectural buffers, resulting in a change in microarchitectural state that can expose sensitive information to an attacker using side-channel analysis. For example, Load Value Injection (LVI) [REF-1202] can exploit direct injection of erroneous values into intermediate load and store buffers. Several conditions may need to be fulfilled for a successful attack: